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| ht49ra1/HT49CA1 remote type 8-bit mcu with lcd rev. 1.00 1 may 7, 2008 general description the ht49ra1/HT49CA1 is a remote type 8-bit mcu 8-bit high performance risc architecture microcontroller. with its internal carrier generator and lcd driver functions the device is is especially suitable for multiple i/o remote control product applications. the usual holtek mcu features such as power down and wake-up functions, oscillator options, etc. combine to ensure user applications require a minimum of external components. the benefits of low power consumption, high perfor- mance, i/o flexibility and low-cost, provide these de- vices with the versatility to suit a wide range of application possibilities such as industrial control, con - sumer products and particularly suitable for use in prod - ucts such as infrared lcd remote controllers and various, subsystem controllers, etc. features operating voltage: 2.0v~3.6v 12 bidirectional i/o lines, 8 input lines, 8 segment output, pc0 (input/output)/rem two external interrupt inputs shared with an i/o line 8-bit programmable timer/event counter with overflow interrupt function single 16-bit programmable timer/event counter with overflow interrupt function rc oscillator and 32768hz crystal oscillator lcd driver with 33 2, 33 3or32 4 segments (c type only), 8 logical output option for seg12~seg19 and 4 i/o port option for seg0~seg3 by changing lcdc register 4096 15 program memory 160 8 data memory real time clock rtc 8-bit prescaler for rtc one carrier output (1 / 2or1 / 3 duty) software lcd, rtc control watchdog timer function power down and wake-up functions to reduce power consumption up to 1 s instruction cycle with 4mhz system clock 4-level subroutine nesting bit manipulation instruction table read instructions 63 powerful instructions all instructions executed in one or two machine cycles low voltage reset/detector function 52-pin qfp, 64-pin lqfp packages technical document tools information faqs application note ha0075e mcu reset and oscillator circuits application note
block diagram note: this block diagram represents the otp devices, for the mask devices there is no device programming circuitry. ht49ra1/HT49CA1 rev. 1.00 2 may 7, 2008 ! " ! # $ % ! & ! # ' device types devices which have the letter r within their part number, indicate that they are otp devices offering the advantages of easy and effective program updates, using the holtek range of development and programming tools. these devices provide the designer with the means for fast and low-cost product development cycles. devices which have the letter c within their part number indicate that they are mask version devices. these devices offer a complementary device for applications that are at a mature state in their design process and have high volume and low cost demands. fully pin and functionally compatible with their otp sister devices, the mask version devices provide the ideal substi - tute for products which have gone beyond their development cycle and are facing cost-down demands. in this datasheet, for convenience, when describing device functions, only the otp types are mentioned by name, however the same described functions also apply to the mask type devices. pin assignment ht49ra1/HT49CA1 rev. 1.00 3 may 7, 2008 ( ) ( * ( + , - . - , / . / , 0 - , 1 / , 2 , ) % - 3 , * , + 3 & 1 1 3 & 2 3 & ) 3 & * 3 & + 3 & 3 & 4 3 & / - 3 & / / 3 & / 0 3 & / 1 3 & / 2 3 & / ) / 0 1 2 ) * + 4 / - / / / 0 / 1 / 2 / ) / * / + / / 4 0 - 0 / 0 0 1 2 1 ) 1 * 1 + 1 1 4 2 2 4 ) - ) / ) 0 0 1 0 2 0 ) 0 * 0 + 0 0 4 1 - 1 / 1 0 1 1 2 - 2 / 2 0 2 1 2 2 2 ) 2 * 2 + 0 3 & 0 / 3 & / - 3 & - 2 1 % / 3 ( - ( / ( 0 ( 1 ( 2 3 & / * 3 & / + 3 & / 3 & / 4 1 3 & 1 0 0 / - 0 / % 0 % / % # ( * ( + , - . - , / . / , 0 - , 1 / , 2 , ) % - 3 , * , + % # % / % 0 / 3 & ) 3 & * 3 & + 3 & 3 & 4 3 & / - 3 & / / 3 & / 0 3 & / 1 3 & / 2 3 & / ) 3 & / * 3 & / + 3 & / 3 & / 4 3 & 0 - 3 & 0 / 3 & 0 0 3 & 0 1 3 & 0 2 3 & 0 ) 3 & 0 * 3 & 0 + 3 & 0 3 & 0 4 3 & 1 - 3 & 1 / 1 3 & 1 0 0 / - 0 3 & 2 1 3 & 1 0 3 & 0 / 3 & / - 3 & - 2 1 % / 3 ( - ( / ( 0 ( 1 ( 2 ( ) / 0 1 2 ) * + 4 / - / / / 0 / 1 0 - 0 / 0 0 0 1 0 2 0 ) 0 * 0 + 0 2 1 2 2 2 ) 2 * 2 + 2 * - * / * 0 * 1 * 2 0 4 1 - 1 / 1 0 1 * 1 + 1 1 4 2 - 2 / 2 0 ) 0 ) 1 ) 2 ) ) ) * ) + ) ) 4 / 2 / ) / * 1 1 1 2 1 ) / + / / 4 2 4 ) - ) / pin description pin name i/o configuration option description pa0~pa7 i/o bidirectional nmos 8-bit input/output port. each bit can be chosen as an nmos output or schmitt trigger input using software instructions. pull-high resistors are permanently connected to these pins. pb0/int0 pb1/int1 pb2/tmr0 pb3/tmr1 pb4~pb7 i wake-up 8-bit schmitt trigger input lines with pull-high resistors. each bit can be con - figured as a wake-up input via configuration options. pins pb0, pb1, pb2 and pb3 are pin-shared with int0, int1, tmr0 and tmr1 respectively pc0/rem i/o carrier output pull-high bidirectional i/o port. pc0 can be configured as a cmos output pin or car - rier output pin using a configuration option. pd0/seg0~ pd3/seg3 i/o bidirectional nmos 4-bit input/output port. each bit can be chosen as an nmos output or schmitt trigger input using software instructions. each pin on this port can be configured either as a segment pin or normal i/o pin us - ing the lcdc register. when used as i/o pins pull-high resistors are perma - nently connected to these pins. osc1 i a resistor is connected between osc1 and ground to implement the internal system clock. osc3 osc4 i o real time clock oscillator. osc3 and osc4 are connected to a 32768hz crystal oscillator for timing purpose. it is not used as the system clock. if the rtc is not selected as f s . then osc3, osc4 should be left floating. vlcd lcd power supply. v lcd should be larger than v dd for connect operation i.e. v lcd v dd v1, v2, c1, c2 lcd voltage pump com0~com2 com3/seg32 o 1 / 2, 1 / 3or1 / 4 duty com0~com2 are the lcd panel common connections. pin com3/seg32 can be setup as an lcd panel segment or as a common output driver via configuration options. seg4~seg11 o lcd panel segments driver outputs. seg12~seg19 o seg12~seg19 cmos output lcd panel segments driver outputs . seg12~seg19 can be setup as lcd segment outputs or as cmos output via a configuration option. seg20~seg31 o lcd panel segments driver outputs. res i schmitt trigger reset input. active low. vdd positive power supply vss negative power supply, ground note: each pin on pb can be programmed through a configuration option to have a wake-up function. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht49ra1/HT49CA1 rev. 1.00 4 may 7, 2008 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.0 3.6 v i dd operating current (rc osc) 3v no load, f sys =4mhz 0.7 1.5 ma i stb1 standby current (*f s =t1) 3v no load, system halt, lcd off at halt 0.1 1 a i stb2 standby current (*f s =32.768khz osc) 3v no load, system halt, lcd on at halt, c type 2.5 5 a i stb3 standby current (*f s =wdt rc osc) 3v no load, system halt lcd on at halt, c type 25 a v il1 input low voltage for i/o ports, tmr0/tmr1 and int0/int1 3v 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr0/tmr1 and int0/int1 3v 0.7v dd v dd v v il2 input low voltage (res )3v 0 0.4v dd v v ih2 input high voltage (res )3v 0.9v dd v dd v i ol1 i/o port & rem sink current 3v v ol =0.1v dd 48 ma i oh1 i/o port & rem source current 3v v oh =0.9v dd 5 7 ma i ol2 lcd common and segment current 3v v ol =0.1v dd 210 420 a i oh2 lcd common and segment current 3v v oh =0.9v dd 80 160 a r ph pull-high resistance of i/o ports 3v 100 150 200 k v lvr low voltage reset voltage lvr 2.1v option 1.98 2.10 2.22 v lvr 3.15v optio 2.98 3.15 3.32 v v lvd low voltage detector voltage lvd voltage 2.2v option 2.08 2.20 2.32 v lvd voltage 3.3v option 3.12 3.30 3.50 v v por vdd start voltage to ensure power-on reset 100 mv r por vdd rise rate to ensure power-on reset 0.035 v/ms note: t sys =1/f sys *f s please refer to wdt clock option ht49ra1/HT49CA1 rev. 1.00 5 may 7, 2008 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 2.0v~ 3.6v 4mhz 3%, temp.= 0 c~50 c 4000 khz 3.0v 4mhz 2%, temp.= 25 c 4000 khz f rtcosc rtc frequency 32768 hz f timer timer i/p frequency (tmr0/tmr1) 3v 0 4000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s t res external reset low pulse width 1 s t lvr low voltage width to reset 0.25 1 2 ms t sst system start-up timer period wake-up from halt 1024 *t sys t int interrupt pulse width 1 s note: *t sys =1/f sys ht49ra1/HT49CA1 rev. 1.00 6 may 7, 2008 ht49ra1/HT49CA1 rev. 1.00 7 may 7, 2008 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the range of devices take ad - vantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o with maximum reli - ability and flexibility. this makes these devices suitable for low-cost, high-volume production for controller appli - cations requiring 4k words of program memory and 160 bytes of data memory storage. clocking and pipelining the main system clock, derived from rc oscillator is subdivided into four internally generated non-overlap - ping clocks, t1~t4. the program counter is incre - mented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instruc - tions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. 5 ! 6 7 8 3 9 ! 6 7 / 8 5 ! 6 7 : / 8 3 9 ! 6 7 8 5 ! 6 7 : 0 8 3 9 ! 6 7 : / 8 : / : 0 7 8 / ! 0 1 2 " ! ! system clocking and pipelining 5 ! 6 / 3 9 ! 6 / 5 ! 6 0 5 " ! / 0 1 2 ) * 3 # ( ; < % ( = > / 0 ? @ ( # # 3 # ( ; # > / 0 ? @ < < . 3 9 ! 6 0 5 ! 6 1 5 ! 6 * 3 9 ! 6 * 5 ! 6 + instruction fetching ht49ra1/HT49CA1 rev. 1.00 8 may 7, 2008 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. for the re - mote type series of microcontrollers with lcd, note that the program counter width varies with the program memory capacity depending upon which device is se - lected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack can have 4 levels is neither part of the data nor part of the program space, and is neither readable nor writable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writable. at a subroutine call or interrupt acknowledge signal, the con - tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig - naled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. mode program counter bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 000000000000 external interrupt 0 000000000100 external interrupt 1 000000001000 timer/event counter 0 overflow 000000001100 timer/event counter 1 overflow 000000010000 time base interrupt 000000010100 rtc interrupt 000000011000 skip program counter + 2 loading pcl pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc11~pc8: current program counter bits @7~@0: pcl bits #11~#0: instruction code address bits s11~s0: stack register bits the program counter is 12 bits wide, i.e. from b11~b0. ht49ra1/HT49CA1 rev. 1.00 9 may 7, 2008 if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper- ations may result in carry, borrow or other status changes, the status register will be correspondingly up- dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. for microcontrollers, two types of program memory are usually supplied. the first type is the one-time programmable, otp, memory where us - ers can program their application code into the device. devices with otp memory are denoted by having an r within their device name. by using the appropriate pro - gramming tools, otp devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. the other type of memory is the mask rom memory, denoted by having a c within the device name. these devices offer the most cost effective solu- tions for high volume products. structure the program memory has a capacity of 4k by 15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the external interrupt. if the ex - ternal interrupt pin int0 on the device receives an ac - tive edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 008h this vector is used by the external interrupt. if the ex - ternal interrupt pin int1 on the device receives an ac - tive edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. - / 2 ? ! ! % - - - ? - - 2 ? - - ? - - ? - / - ? 1 5 5 ? / ) - - ? 5 5 5 ? 1 - - ? + 5 5 ? 2 - - ? , ! " % - / ? 3 ' ! ! - ! " % 3 ' ! ! / ! " % 3 9 ! ! " - % 3 9 ! ! " / % ! " % program memory structure ! # ' / # ' 0 # ' 1 # ' 2 " a ! , a ht49ra1/HT49CA1 rev. 1.00 10 may 7, 2008 location 00ch this internal vector is used by the timer/event coun - ter 0. if a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. location 010h this internal vector is used by the timer/event coun - ter 1. if a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. location 014h this internal vector is used by the time base interrupt. if a time base interrupt occurs, the program will jump to this location and begin execution if the time base in - terrupt is enabled and the stack is not full. location 018h this internal vector is used by the real time clock in - terrupt. the program will jump to this location and be - gin execution when a real time clock interrupt signal is generated if the interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0 . the following diagram illustrates the addressing/data flow of the look-up table: table program example the following example shows how the table pointer and table data is defined and retrieved from the ht49ra1 microcontroller. this example uses raw table data lo - cated in the last page which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k program memory of the ht49ra1 microcontroller. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data table will be at the program memory address f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m]1111@7@6@5@4@3@2@1@0 table location note: pc11~pc8: current program counter bits @7~@0: table pointer tblp bits the table address location is 12 bits, i.e. from b11~b0. ! ? , , # , # ? " a > @ ! ! ? , ! ! # $ , ht49ra1/HT49CA1 rev. 1.00 11 may 7, 2008 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org f00h ; sets initial address of last page (for ht49ra1) dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : data memory the data memory is a volatile area of 8-bit wide ram in- ternal memory and is the location where temporary in- formation is stored. divided into three sections, the first of these is an area of ram where special function regis- ters are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the third area is reserved for the lcd memory. this special area of data memory is mapped directly to the lcd display so data written into this memory area will directly affect the displayed data. the addresses of the lcd memory area overlap those in the other memory areas, switching between the two areas is achieved by setting the bank pointer to the cor - rect value. structure the special purpose and general purpose data mem - ory are located at consecutive locations. all are imple - mented in ram and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. the start address of the data memory for all devices is the address 00h. registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. the lcd data memory is mapped into bank 1 of the data memory, however, only the lower four bits are used. the higher four bits, if read by the program will return a zero value. the start of lcd data memory for all devices is the address 40h. however, since the lcd data memory is located in bank 1, to access this area the bank pointer must first be set to a value of 01h. note that after power-on the contents of the data memory, including - - ? ) 5 ? 5 5 ? / 5 ? , ! - , ! / , ! / # , ! - & ! " * - ? 2 - ? * - ? " " data memory structure note: most of the data memory bits can be directly manipulated using the set [m].i and clr [m].i with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer registers ht49ra1/HT49CA1 rev. 1.00 12 may 7, 2008 the lcd data memory, will be in an unknown condition, the programmer must therefore ensure that the data memory is properly initialised. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. as the general purpose data memory exists in bank 0, it is necessary to first ensure that the bank pointer is set to the correct value before accessing the general purpose data memory. when the bank pointer is set to the value 01h, the lcd memory will be accessed. bank 1must be addressed indirectly using the memory pointer mp1 and the indirect addressing register iar1. any direct addressing or any indirect ad - dressing using mp0 and iar0 will always result in data from bank 0 being accessed. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant spe - cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . lcd memory the data to be displayed on the lcd is also stored in an area of fully accessible data memory. by writing to this area of ram, the lcd display output can be directly con - trolled by the application program. as the lcd memory exists in bank 1, but have addresses which map into the bank 0 data memory, it is necessary to first ensure that the bank pointer is set to the value 01h before accessing the lcd memory. the lcd memory can only be ac - cessed indirectly using the memory pointer mp1 and the indirect addressing register iar1. when the bank pointer is set to bank 1 to access the lcd data memory. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory be- gins at the address 00h . any unused data memory lo- cations between these special function registers and the point where the general purpose memory begins is re- served for future expansion purposes, attempting to read data from these locations will return a value of 00h . indirect addressing register iar0, iar1 the iar0 and iar1 registers, located at data memory addresses 00h and 02h , are not physically imple - mented. these special function registers allows what is known as indirect addressing, which permits data ma - nipulation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined. any actions on the iar0 and iar1 registers will result in corresponding read/write operations to the memory locations specified by the memory pointers mp0 and mp1. reading the iar0 and iar1 registers indirectly will return a result of 00h and writing to the register indirectly will result in no operation. < ! = b - - b ( - - ( / / , ( # , # , # ? ( . - - - / ? / # / ( , . / # special purpose data memory ht49ra1/HT49CA1 rev. 1.00 13 may 7, 2008 memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank0, while mp1 and iar1 are used to access data from bank0 and bank1. the following example shows how to clear a section of four ram locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. bank pointer bp in the data memory area it should be noted that both the lcd memory and the other data memory share the same addresses. therefore when using instructions to access the lcd memory or the general purpose data memory, it is necessary to ensure that the correct area is selected. the general purpose is located in bank 0 while the lcd memory is located in bank 1. selecting the correct data memory area is achieved by using the bank pointer. if data in bank 0 is to be accessed then bp should be cleared to zero, while if the lcd memory is to be accessed, which is located in bank 1, then bp should be loaded with a value of 01h. it must be noted that data in bank 1can only be accessed indirectly using the mp1 memory pointer and the iar1 indirect addressing regis - ter. any direct addressing or any indirect addressing us - ing mp0 and iar0 will always result in data from bank 0 being accessed. the data memory bank pointer is in - itialised to bank 0 after a reset, except for the wdt time-out reset in the power down mode, in which case, the data memory bank pointer remains unchanged. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within either bank 0 or bank 1. accumulator acc the accumulator is central to the operation of any and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate re - sults from the alu are stored. without the accumulator it would be necessary to write the result of each calcula - tion or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher pro - gramming and timing overheads. data transfer opera - tions usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is nec - essary to do this by passing the data through the accu - mulator as no direct transfer between two registers is permitted. + - , - , - - , ! - / , ! / # . = b - b bank pointer register ht49ra1/HT49CA1 rev. 1.00 14 may 7, 2008 program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the pro - gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage- ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical opera - tion is zero; otherwise z is cleared. ov is set if an operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut- ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. real time clock control register rtcc the rtcc register controls two internal functions one of which is the real time clock (rtc) interrupt, whose function is to provide an internal interrupt signal at regu - lar fixed intervals. the driving clock for the rtc interrupt comes from the internal clock source, known as f s , which is then further divided to give longer time values, which in turn generates the interrupt signal. the value of this division ratio is determined by the value pro - grammed into bits 2~0, known as rt2~rt0, of the rtcc register. by writing a value directly into these 5 % c ( ! " # $ " a ( 9 a c a ' a $ a % & " # " # $ " $ $ ! a a . " ! = b - b + - status register ht49ra1/HT49CA1 rev. 1.00 15 may 7, 2008 rtcc register bits, time-out values from 2 8 /f s to 2 15 /f s can be generated. the rtcc register also controls the quick start up function of the rtc oscillator. this oscilla - tor, which has a fixed frequency of 32768hz, can be made to start up at a quicker rate by setting bit 4, known as the qosc bit to 0 . this bit will be set to a 0 value when the device is powered on, however, as some extra power is consumed, the qosc bit should be set to 1 after about 2 seconds to reduce power consumption. interrupt control register intc0, intc1 these 8-bit registers, known as intc0 and intc1, con- trol the operation of both the external and internal inter - rupts. by setting various bits within these registers using standard bit manipulation instructions, the enable/dis - able function of the external interrupts and each of the internal interrupts can be independently controlled. a master interrupt bit within these registers, the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to disable further in - terrupt and is set by executing the reti instruction. lcdc register lcdc the lcdc register is used as the control register for the lcd panel. the lcden bit is the overall on/off control for the lcd driver and can be used to power down the driver and thus used to conserve power when the lcd is not used. as four segment lines are also pin-shared with four port pd lines, bits segpt0~segpt3 in the lcdc register are used to determine which function is chosen, either lcd segment line or normal i/o line. this register also contains a bit to control the rtc on/off enable. the rtc on/off control is however also dependent upon which clock is chosen as the internal fs clock source. the accompanying table shows the overall rtc control operation. ! " + - 0 / - 0 - - - - / / / / / - - / / - - / / - - / - / - / - / 0 a 0 4 a 0 / - a 0 / / a 0 / 0 a 0 / 1 a 0 / 2 a 0 / ) a # $ % ! / < ! - < d / < - < ! # $ % " / < $ ' - < ! ' . " ! = b - b " $ $ ' # $ # % # % d rtcc register lcden and rtcen may decide lcd and rtc on/off condition on normal operation. f s clock source lcd/rtc control bits lcden, rtcen=0, 0 lcden, rtcen=0, 1 lcden, rtcen=1, 0 lcden, rtcen=1, 1 f sys /4 lcd off, rtc off lcd off, rtc off lcd on, rtc off lcd on, rtc off wdt osc lcd off, rtc off lcd off, rtc off lcd on, rtc off lcd on, rtc off rtc osc (wdt enable) lcd off, rtc on lcd off, rtc on lcd on, rtc on lcd on, rtc on rtc osc (wdt disable) lcd off, rtc off lcd off, rtc on lcd on, rtc on lcd on, rtc on ht49ra1/HT49CA1 rev. 1.00 16 may 7, 2008 timer/event counter 0/1 registers tmr0, tmr0c, tmr1h, tmr1l, tmr1c all devices possess a single internal 8-bit count-up timer. an associated register known as tmr0 is the lo - cation where the timer s 8-bit value is located. this reg - ister can also be preloaded with fixed data to allow different time intervals to be setup. an associated con - trol register, known as tmr0c, contains the setup infor - mation for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. all devices possess a single internal 16-bit count-up timer. an associated register known as tmr1h, tmr1l is the location where the timer s 16-bit value is located. this register can also be preloaded with fixed data to al - low different time intervals to be setup. an associated control register, known as tmr1c, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pc and pd. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. one flexible feature of these registers is the ability to directly program single bits us- ing the set [m].i and clr [m].i instructions. the pc port also has a control register known as pcc, and has the ability to change its i/o pin from output to input and vice versa by manipulating the bit in the register. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. although port b remains fixed as an input only port, all pins on port a, port c and port d, have the ability to function as either input or output. the device provides 13 bidirectional input/output lines and 8 input lines. the i/o ports are known as port a, port c and port d and the input port is known as port b. these ports are mapped to the data memory with spe - cific addresses as shown in the special purpose data memory table. the port a and port d i/o ports can be used for both input and output operations, however, it must be noted that unlike port c, they do not have port control registers. setting up an pa or pd port pin as an input is achieved by first setting its output high which ef - fectively places its nmos output transistor in a high im - pedance state allowing the pin to be now used as an input. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port ad - dress. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all pins on port a, port b and port d have a permanently connected pull high resistor. the pull high resistor on port c is chosen via a configuration option. these pull-high resistors are implemented using a weak pmos transistor. port b wake-up the device has a halt instruction enabling the microcontroller to enter a power down mode and pre- serve power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port b pins from high to low. after a halt instruction forces the microcontroller into entering a halt condition, the processor will re - main idle or in a low-power state until the logic condition of the selected wake-up pin on port b changes from high to low. this function is especially suitable for applica - tions that can be woken up via external switches. note that each pin on port b can be selected individually to have this wake-up feature. d e d " ( - f ( + - f 1 % " , pa, pd input/output ports , " , - f , + % " " ! " . - a , - . / a , / - a , 0 / a , 1 pb input port ht49ra1/HT49CA1 rev. 1.00 17 may 7, 2008 i/o port control registers the register pcc is used to control the input/output con - figuration of port pc. with this control register, this sin - gle cmos output or input with or without pull-high resistor structures can be reconfigured dynamically un - der software control. the pin of the port c i/o port is di- rectly mapped to a bit in its associated pcc port control register. for the i/o pin to function as an input, the corre- sponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the correspond- ing bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control. external interrupt input the external interrupt pin int0 or int1 are pin-shared with the i/o pin pb0 or pb1. for applications not re - quiring an external interrupt input, the pin-shared ex - ternal interrupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bits in the intc0 register must be disabled. external timer clock input the external timer pin tmr0 or tmr1 are pin-shared with the i/o pin pb2 or pb3. to configure it to operate as a timer input, the corresponding control bits in the timer control register must be correctly set. for appli - cations that do not require an external timer input, the pin can be used as a normal i/o pin. note that if used as a normal i/o pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the in- put pin from interfering with the timer operation. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. programming considerations within the application program, one of the first things to consider is port initialization. after a reset,the i/o port registers will be set high. it is important to note that for the nmos types, when set high the output nmos tran - sistor will be placed into a high impedance condition, al - lowing the pin to be used also as an input. the generation of a high level on the nmos outputs there - fore is reliant upon externally connected circuitry and the pull-high resistor. / 0 1 2 / 0 1 2 a read/write timing % g g - 3 d e d e d ! , ? " ! , ! " ! , - 3 d 3 / pc0 input/output port ht49ra1/HT49CA1 rev. 1.00 18 may 7, 2008 when using the pin as an output, its logic level can be setup by loading byte wide data into the appropriate port register or by programming individual bits in these regis - ters, using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. however, in the case of nmos type pins, there are some special consid - erations that must be noted. in the case of an nmos pin that is set high by the microcontroller, i.e. placed into a high impedance condition, but driven low by externally connected circuitry, this pin would be read as being in a low condition during the read phase of the set [m].i and clr [m].i instructions. when the ensuing write phase occurs, this pin, having been read as being in a low condition during the read phase, would then be con - sequently erroneously set low. for this reason great care must be taken when using these bit control instruc - tions with nmos output types. port b has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port b pins. single or multiple pins on port b can be setup to have this function. liquid crystal display (lcd) driver for large volume applications, which incorporate an lcd in their design, the use of a custom display rather than a more expensive character based display reduces costs significantly. however, the corresponding signals required, which vary in both amplitude and time, to drive such a custom display require many special consider - ations for proper lcd operation to occur. this device in - cludes internal lcd signal generating circuitry and various configuration options, which will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom lcds. lcd memory the device provides a specific area of data memory for the lcd data. this data area is known as the lcd mem - ory. any data written here will be automatically read by the internal lcd driver circuits, which will in turn auto - matically generate the necessary lcd driving signals. therefore any data written into the lcd memory will be immediately reflected into the actual lcd display con - nected to the microcontroller. the start address of the lcd memory is 40h, the end address of the lcd mem - ory is 60h. as the lcd data memory addresses overlap those of the general purpose data memory, the lcd data mem - ory is stored in its own memory data bank, which is dif - ferent from that of the general purpose data memory. the lcd data memory is stored in bank 1. the data memory bank is chosen by using the bank pointer, which is a special function register in the data memory, with the name, bp. when the lowest bit of the bank pointer have the binary value 0 , only the general pur- pose data memory will be accessed, no read or write actions to the lcd memory will take place. to access the lcd memory therefore requires first that bank 1 is selected by setting the lowest bit of the bank pointer to ( + 3 ! / < ! - < # 3 ! / < ! - < . " ! = b - b 3 & - - " ! a ! ! / < - - < 3 & - 3 & / / " ! a ! ! / < / - < 3 & / 3 & 0 0 " ! a ! ! / < 0 - < 3 & 0 3 & 1 1 " ! a ! ! / < 1 - < 3 & 1 - # 3 . 3 . 3 & - 3 & / 3 & 0 3 & 1 lcd control register lcdc ht49ra1/HT49CA1 rev. 1.00 19 may 7, 2008 the binary value 1 . after this, the lcd memory can then be accessed by using indirect addressing through the use of memory pointer mp1. with bank 1 selected, then using mp1 to read or write to the memory area, 40h~60h, depending upon which device is chosen, will result in operations to the lcd memory. directly ad- dressing the lcd memory is not applicable and will re- sult in a data access to the bank 0 general purpose data memory. the accompanying diagrams show the lcd memory map for the 33 2, 33 3or32 4 format pixel drive capa- bility. the 4-com format will be automatically setup if the 1 / 4 duty configuration option is selected while the 3-com format will be automatically setup if the 1 / 2or 1 / 3 duty configuration option is selected. lcd control register lcdc the device contains a single register known as, lcdc, which is used to control some internal lcd driver func - tions. the lcden bit is the overall on/off control for the lcd driver and can be used to power down the driver and thus used to conserve power when the lcd is not used. as four segment lines are also pin-shared with four port pd lines, bits segpt0~segpt3 in the lcdc register are used to determine which function is chosen, either lcd segment line or normal i/o line. lcd clock the lcd clock is driven by the internal clock source f s , which can originate from either the wdt oscillator, the rtc oscillator or f sys /4, the choice of which is deter - mined by a configuration option. for proper lcd opera - tion, this f s internal clock source then passes through a divider, to provide an lcd clock source frequency as near as possible to 4khz. f s clock source lcd clock selection wdt oscillator wdt/2 2 rtc oscillator rtc/2 3 f sys /4 lcd clock frequency selection the available division ratios, however, depends on the clock source that is used for the internal clock source, f s . if the clock source for f s originates from the wdt oscilla - tor, then only a fixed division ratio of f s /2 2 is available. if the clock source for f s originates from the rtc oscilla - tor, then only one division ratio of f s /2 3 is available. how - ever, if the clock source for f s originates from f sys /4, then a range of lcd clock frequencies are available from f s /2 2 to f s /2 8 , the value of which is selected by a fur - ther available configuration option. these ratios ensure that for proper lcd operation, a signal frequency as near as possible to 4khz, can be selected. for an lcd clock frequency of 4khz, the microcontroller lcd driver circuitry will generate an lcd frame frequency between 55hz and 62hz. this is in line with the general lcd op - erating frequency range which lies between 25hz and 250hz. note that if the selected lcd clock frequency is too high, this will result in a higher than required frame frequency and give rise to higher power consumption while selecting a too low frequency may result in flicker. it is therefore important that if f sys /4 is used as the clock source for f s , the correct configuration option should be chosen to obtain an lcd clock frequency as close to 4khz as possible. < ! b - b 2 - ? * - ? + * ) 2 1 0 / - 3 & - 3 & 1 0 - / 0 2 / ? 3 & / 2 - ? * - ? + * ) 2 1 0 / - 3 & - 3 & 1 0 - / 0 1 2 / ? 3 & / 3 & 1 / ) 5 ? ) 5 ? 3 & 1 / ) * ( + % , ) ( + % , lcd memory map a ; 2 0 0 a ; 2 0 f ht49ra1/HT49CA1 rev. 1.00 20 may 7, 2008 lcd driver output the number of com and seg outputs supplied by the lcd driver, as well as its biasing and duty options, are dependent upon the configuration options selected. the accompanying table lists the various options for each of the devices. duty driver number bias bias type 1 / 2 33 2 1 / 2or1/3 c type 1 / 3 33 3 1 / 2or1/3 c type 1 / 4 32 4 1 / 2or1/3 c type lcd driver outputs, duty and bias options the nature of liquid crystal displays require that only ac voltages can be applied to their pixels as the applica - tion of dc voltages to lcd pixels will cause permanent damage. for this reason the relative contrast of an lcd display is controlled by the actual rms voltage applied to each pixel, which is equal to the rms value of the voltage on the com pin minus the voltage applied to the seg pin. this differential rms voltage must be greater than the lcd saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. the requirement to limit the dc voltage to zero and to control as many pixels as possible with a minimum num - ber of connections, requires that both a time and ampli - tude signal is generated and applied to the application lcd. these time and amplitude varying signals are au - tomatically generated by the lcd driver circuits in the microcontroller. what is known as the duty determines the number of common lines used, which are also known as backplanes or coms. the duty, which is cho - sen by a configuration option to have a value of 1 / 2, 1 / 3 or 1 / 4 and which equates to a com number of 2, 3 and 4 respectively, therefore defines the number of time divi - sions within each lcd signal frame. the accompanying timing diagrams depict the lcd signals generated by the microcontroller for various values of duty and bias. - ! . / ! . ( ! . % ( % , % % ( % , % % ( % , % - / ( ! 5 5 % ( % , % % ( % , % % ( % , % - " $ ! " # & . - = / ( ! " % ( % , % % ( % , % / 5 ( + # # & . lcd driver output (1 / 2 duty, 1 / 2 bias) note for 1 / 2 bias, the va=vlcd and vb=vlcd 1 / 2 the lcd function can be optioned as on or off during the power down mode by a configuration option. ht49ra1/HT49CA1 rev. 1.00 21 may 7, 2008 - " $ ! " # & . ( + # # & . - = / = 0 ( ! " - / 0 ( ! 5 5 - ! . / ! . 0 ! . - = / ! . - = 0 ! . / = 0 ! . ( ! . % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % % ( % , % / 5 lcd driver output (1 / 3 duty, 1 / 2 bias) note: for 1 / 2 bias, the va=vlcd and vb=vlcd 1 / 2 the lcd function can be optioned as on or off during the power down mode by a configuration option. ht49ra1/HT49CA1 rev. 1.00 22 may 7, 2008 % ( % , % % / 5 % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % - / 0 ( ! 5 5 - ! . 1 / ! . 0 ! . 7 ! ! 8 - = / ! . 1 ! . - " $ ! " # & . ( + # # & . - = / = 0 = 1 ( ! " % ( % , % % % ( % , % % % ( % , % % - = 0 ! . % ( % , % % - = 1 ! . % ( % , % % ( ! . lcd driver output (1 / 4 duty, 1 / 3 bias) note: for 1 / 3 bias va=vlcd 1.5, vb=vlcd and vc=vlcd 1 / 2. the lcd function can be optioned as on or off during the power down mode by a configuration option. ht49ra1/HT49CA1 rev. 1.00 23 may 7, 2008 % ( % , % % / 5 % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % % ( % , % % - / 0 ( ! 5 5 - ! . / ! . 0 ! . - = 0 ! . - = / ! . % ( % , % % / = 0 ! . % ( % , % % ( ! . - " $ ! " # & . ( + # # & . - = / = 0 ( ! " % ( % , % % % ( % , % % lcd driver output (1 / 3 duty, 1 / 3 bias) note: for 1 / 3 bias the va=vlcd 1.5, vb=vlcd and vc=vlcd 1 / 2. the lcd function can be optioned as on or off during the power down mode by a configuration option. ht49ra1/HT49CA1 rev. 1.00 24 may 7, 2008 % ! * " % # - 6 / 5 - 6 / 5 - 6 / 5 " / 0 % / % 0 % ( % , % 7 h % # / 6 ) 8 7 h % # 8 7 h % # 6 ) 8 # $ " " % ! " % # - 6 / 5 - 6 / 5 - 6 / 5 " / 0 % / % 0 % ( % , 7 h % # 8 7 h % # 6 ) 8 # $ " " c type bias voltage levels lcd voltage source and biasing the time and amplitude varying lcd signals generated by the microcontroller require the generation of several voltage levels for their operation. the number of voltage levels used by the signal depends upon device and the chosen bias configuration options. lcd biasing the device has a configuration option to select either 1 / 2or1 / 3 bias. for the 1 / 2 bias configuration option, three voltage levels vss, va and vb are utilised. vb is generated internally by the microcontroller and will have a value equal to vlcd/2. for the 1/3 bias option, four voltage levels vss, va, vb and vc are utilised. an ex - ternal lcd voltage source is also provided on pin vlcd to generate these voltages. as the c type bias option uses a charge pump circuit, higher voltages than what is provided externally on vlcd can be generated. this feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the lcd. as the lcd driver ha s a c type bias, a charge-pump ca - pacitor between pins c1 and c2 and filter capacitors on pins v1 and v2 are required to generate the necessary voltage levels. programming considerations certain precautions must be taken when programming the lcd. one of these is to ensure that the lcd memory is properly initialized after the microcontroller is pow- ered on. like the general purpose data memory, the contents of the lcd memory are in an unknown condi- tion after power-on. as the contents of the lcd memory will be mapped into the actual lcd, it is important to ini- tialize this memory area into a known condition soon af - ter applying power to obtain a proper display pattern. consideration must also be given to the capacitive load of the actual lcd used in the application. as the load presented to the microcontroller by lcd pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is partic - ularly true in the case of the com lines which may be connected to many lcd pixels. the accompanying dia - gram depicts the equivalent circuit of the lcd. setting the correct frequency of the lcd clock is an - other factor which must be taken into account in user ap - plications. to have the lcds operate at their best frame frequency, which is normally between 25hz and 250hz, it is important to select an appropriate lcd clock fre - quency configuration option. the correct option should be chosen to ensure that an lcd clock frequency as close to 4khz as possible is achieved. with such a fre- quency chosen, the microcontroller internal lcd driver circuits will ensure that the appropriate lcd driving sig- nals are generated to obtain a suitable lcd frame fre- quency. note that as the lcd driver will consume a certain amount of power it can be disabled using the lcden bit in the lcdc register. in battery applications where power consumption is an important consideration to prolong battery life, this bit should be used to power down the lcd circuitry to conserve power. - / 0 1 3 & - 3 & / 3 & 0 3 & ! lcd panel equivalent circuit ht49ra1/HT49CA1 rev. 1.00 25 may 7, 2008 timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the devices contain one 8-bit and one 16-bit count-up timers. as each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. there are two types of registers related to the timer/event counters. the first is the register that con - tains the actual value of the timer and into which an ini - tial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and deter - mines how the timer is to be used. all devices can have the timer clock configured to come from the internal clock source. in addition, the timer clock source can also be configured to come from an external timer pin. configuring the timer/event counter input clock source the internal timer s clock can originate from various sources, depending upon which timer is chosen. the system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. an external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin tmr0 or tmr1, depending upon which timer is used. depending upon the condition of the t0e or t1e bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer registers tmr0, tmr1h, tmr1l the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. these registers are known as tmr0, tmr1h or tmr1l, depending upon which de - vice is used. the value in the timer registers increases by one each time an internal clock pulse is received or an ex - ternal transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload regis - ter to the full count of ffh or ffffh at which point the timer overflows and an internal interrupt signal is gener - ated. the timer value will then be reset with the initial preload register value and continue counting. note that to achieve a maximum full range count of ffh or ffffh, the preload register must first be cleared to all zeros. it should be noted that after power-on, the preload registers will be in an unknown condition. note that if the timer/event counters are in an off condition and data is written to their preload registers, this data will be immediately written into the actual counter. how- ever, if the counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the actual counter the next time an over- flow occurs. - - 3 3 ' ! ! ! - . 3 ' ! ! , ' a $ ! " , 3 ' ! ! - / - - a ; 2 a ; - g " ! ! " timer/event counter 0 structure / / 3 3 ' ! ! ! / * , , ' a $ ! " # $ , , a a / / / - / . ? , # $ , / * , 3 ' ! ! / g a ; 2 1 0 + * ? i timer/event counter 1 structure ht49ra1/HT49CA1 rev. 1.00 26 may 7, 2008 for the 16-bit timer/event counter which has both low byte and high byte timer registers, accessing these reg - isters is carried out in a specific way. it must be noted when using instructions to preload data into the low byte timer register, namely tmr1l, the data will only be placed in a low byte buffer and not directly into the low byte timer register. the actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely tmr1h, is executed. on the other hand, using instruc - tions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. at the same time the data in the low byte buffer will be transferred into its associated low byte timer register. for this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. it must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associ - ated low byte buffer. after this has been done, the low byte timer register can be read in the normal way. note that reading the low byte timer register will result in read - ing the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control registers tmr0c, tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. it is the timer control register together with its corre- sponding timer registers that control the full operation of the timer/event counters. before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to en - sure its correct operation, a process that is normally car - ried out during program initialisation. to choose which of the three modes the timer is to oper - ate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair t0m1/t0m0 or t1m1/t1m0 respectively, depend - ing upon which timer is used, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as t0on or t1on, depend - ing upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. if the timer is in the event count or pulse width measure - ment mode, the active transition edge level type is se - lected by the logic level of bit 3 of the timer control register which is known as t0e or t1e depending upon which timer is used. configuring the timer mode in this mode, the timer can be utilized to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. to operate in this mode, the bit pair, t0m1/t0m0 or t1m1/t1m0 depending upon which timer is used, must be set to 1 and 0 respectively. in this mode the internal clock is used as the timer clock. the timer-on bit, t0on or t1on, depending upon which timer is used, must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will preload the value already loaded into the preload register and continue counting. a timer overflow condi- tion and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the et0i or et1i bits of the intc0, intc1 register are reset to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be re - corded by the internal timer. for the timer to operate in the event counting mode, the bit pair, t0m1/t0m0 or t1m1/t1m0 depending upon which timer is used, must be set to 0 and 1 respectively. the timer-on bit t0on or t1on depending upon which timer is used, must be set high to enable the timer to count. depending upon which counter is used, if t0e or t1e is low, the counter will in - crement each time the external timer pin receives a low ! ! ! " : / : 0 : . : . : / timer mode timing chart : 0 3 9 ! 3 ' ! ! ! ! : 1 : / event counter mode timing chart ht49ra1/HT49CA1 rev. 1.00 27 may 7, 2008 + / 3 / . / - / / - / 0 # + # # $ & . " ! = b - b 3 ' ! ! ' / < ! ! a ! - < ! ! ! ! ' / < ! ! ! ! = " ! a ! - < ! ! ! a ! = " ! ! 3 ' ! ! ! ! ! / < ! - < / / - - / / / - - / - / ! ' ' ! ! " $ ! " ! / < 1 0 + * ? i - < a ; 2 / timer/event counter 1 control register tmr1c to high transition. if t0e or t1e is high, the counter will increment each time the external timer pin receives a high to low transition. as in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. the counter will then preload the value already loaded into the preload register. as the external timer pins are pin-shared with other i/o pins, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the t0m1/t0m0 or t1m1/t1m0 bits place the timer/event counter in the event counting mode, the second is to en - sure that the port control register configures the pin as an input. it should be noted that a timer overflow is one of the interrupt and wake-up sources. note that the timer interrupts can be disabled by ensuring that the et0i or et1i bits in the intc0 or intc1 register are reset to zero. / 0 # + # # $ & 1 3 ' ! ! ' / < ! ! a ! - < ! ! ! - 3 ' ! ! ! ! ! / < ! - < " ! - / - - / / - - - / - / ! ' ' ! ! " $ ! ! ' / < ! ! ! ! = " ! a ! - < ! ! ! a ! = " ! ! / < " ! - < ! " . " ! = b - b + - 3 - . - - - / - timer/event counter 0 control register tmr0c ht49ra1/HT49CA1 rev. 1.00 28 may 7, 2008 configuring the pulse width measurement mode in this mode, the width of external pulses applied to the external timer pin can be measured. in the pulse width measurement mode the timer clock source is supplied by the internal clock. for the timer to operate in this mode, the bit pair, t0m1/t0m0 or t1m1/t1m0, depend - ing upon which timer is used, must both be set high. de - pending upon which counter is used, if the t0e or t1ebit is low, once a high to low transition has been received on the external timer pin, the timer will start counting un - til the external timer pin returns to its original high level. at this point the t0on or t1on bit, depending upon which counter is used, will be automatically reset to zero and the timer will stop counting. if the t0e or t1e bit is high, the timer will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the t0on or t1on, bit will be automatically reset to zero and the timer will stop counting. it is important to note that in the pulse width measurement mode, the t0on or t1on bit is automati - cally reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the t0on or t1on bit can only be reset to zero under program control. the re - sidual value in the timer, which can now be read by the program, therefore represents the length of the pulse re- ceived on the external timer pin. as the t0on or t1on bit has now been reset, any further transitions on the ex- ternal timer pin, will be ignored. not until the t0on or t1on bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the counter is con- trolled by logical transitions on the external timer pin and not by the logic level. as in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. the counter will also be reset to the value already loaded into the preload register. if the external timer pin is pin-shared with other i/o pins, to ensure that the pin is configured to operate as a pulse width measuring input pin, two things have to happen. the first is to ensure that the t0m1/t0m0 or t1m1/t1m0 bits place the timer/event counter in the pulse width measuring mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that a timer overflow and corresponding timer interrupt is one of the wake-up sources. note that the timer interrupts can be disabled by ensuring that the et0i or et1i bits in the intc0 or intc1 register are reset to zero. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quire the use of the external pin for correct operation. as this pin is a shared pin it must be configured correctly to ensure it is setup for use as a timer/event counter input and not as a normal i/o pin. this is implemented by en - suring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. additionally the port control register must be set high to ensure that the pin is setup as an input. any pull-high resistor on this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an inter- nal interrupt signal directing the program flow to the re- spective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not syn- chronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring pro - grammers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. : / : 0 : 1 : 2 3 9 ! - / ! ! " - . / . 7 $ - 3 / 3 h - 8 " ! ! ! " " ' a ! a / 6 pulse width measure mode timing chart ht49ra1/HT49CA1 rev. 1.00 29 may 7, 2008 when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly in - itialised before using them for the first time. the associ - ated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control regis - ter must also be correctly set to ensure the timer is prop - erly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg - isters are unknown. after the timer has been initialised the timer can be turned on and off by controlling the en - able bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer oper - ation if executed as a single timer control register byte write instruction. when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irre - spective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condi - tion. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter - nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the inter - rupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector reti org 0ch ; timer/event counter 0 interrupt vector jmp tmrint ; jump here when timer overflows : org 20h ; main program ;internal timer/event counter 0 interrupt routine tmrint: : ; timer/event counter 0 main program placed here : reti : : begin: ;setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a; mov a,080h ; setup timer 0 control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,009h ; enable master interrupt and timer interrupt mov int0c,a set tmr0c.4 ; start timer/event counter 0 - note mode bits must be previously setup ht49ra1/HT49CA1 rev. 1.00 30 may 7, 2008 carrier generator some remote control transmitter applications require a carrier frequency generator to transmit the remote con - trol signal at the appropriate frequency to the receiving device. these devices include an internal carrier fre - quency generator for this purpose, the frequency of which is specified by selecting the correct configuration options. this carrier signal is supplied on the rem pin, which is also pin-shared with pc0. the selection of the required function, whether remote output or cmos output, is im - plemented by selecting the required configuration op - tion. if the remote output rem is selected by configuration option, the rem output will be activated if the pc0 data bit in the pc register is set to high. this output data bit is used as the on/off control bit for the rem output. note that the rem output will be low if the pc0 output data bit is set to zero. however, if the line is configured as a pc0 output pin it will switch to a high level and remain so until the application program resets the pin to a zero. it is therefore important to note that, for otp devices, if the pin is configured as a pc0 output pin, and a npn transistor is connected to this output to drive an infrared led, the led will be turned on during this power-on reset period. for general purpose remote controller applications, it is therefore recommended that the rem configuration option is selected together with an external npn transistor to drive the infrared led. the clock source for the carrier generator is supplied by the system clock divided by 4. by selecting values for m and n using configuration options in association with the following equation the required carrier frequency can be generated. carrier frequency clock source mx2 n the value of m can be either 2 or 3 while the value of n can range from 0 to 3, both values are chosen by se - lecting the required configuration options. if m is equal to 2 the duty cycle of the output waveform will always be equal to 1/2. if m is equal to 3 , with the exception of n being equal to 0 , the duty cycle can be either 1/2 or 1/3, the actual value of which is determined by config - uration options. m 2 n duty cycle 2, 4, 8, 16 1 / 2 31 / 3 6, 12, 24 1 / 2or1 / 3 the following table shows examples of different carrier frequencies: f sys f carrier duty m 2 n 455khz 37.92khz 1/3 only 3 56.9khz 1/2 only 2 a ; 2 1 ! ! a ! " ! 5 j ! ' - 3 - / 0 / 1 ! a 6 " ! ! a ! " ! carrier signal generation ht49ra1/HT49CA1 rev. 1.00 31 may 7, 2008 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter, time base or rtc inter - rupt requires microcontroller attention, their correspond - ing interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct atten - tion to their respective needs. the device contains two external interrupts and four internal interrupt functions. the external interrupt is controlled by the action of the ex - ternal int0, int1 pin, while the internal interrupts are controlled by the two timer/event counter overflows, the time base interrupt and the rtc interrupt. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the intc0 and intc1 registers, which are located in the data memory. by controlling the appropriate enable bits in these regis - ter each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding re - quest flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a timer/event counter overflow, time base or rtc overflow or the external interrupt line being triggered will all generate an interrupt request by setting their corre- sponding request flag, if their appropriate interrupt en- able bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new ad- dress which will be the value of the corresponding inter- rupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority external interrupt 0/1 1/2 timer/event counter 0/1 overflow 3/4 time base interrupt 5 real time clock interrupt 6 external interrupt for an external interrupt to occur, the global interrupt enable bit, emi, and external interrupt enable bit, eei0, eei1, must first be set. additionally the correct interrupt edge bit must be selected to enable the external interrupt function and to choose the trigger edge type. an actual external interrupt will take place when the external interrupt request flag, eif0 or eif1, is set, a situation that will occur when a transition, whose type is chosen by configuration option appears on the int0 and, int1 pins. the external interrupt pins are pin-shared with the i/o pins pb0 and pb1 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the intc0 register have been set. the pins must also be setup as inputs. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the relevant external interrupt vectors at locations 04h and 08h, will take place. when the interrupt is serviced, the external interrupt request flag, eif0, eif1, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. ht49ra1/HT49CA1 rev. 1.00 32 may 7, 2008 2 - 1 ! " ! / < ! - < 3 9 ! ! " - ! / < ! - < 3 9 ! ! " / ! / < ! - < 3 ' ! ! - ! " ! / < ! - < 3 9 ! ! " - j a / < ' - < ! ' 3 9 ! ! " / j a / < ' - < ! ' 3 ' ! ! - ! " j a / < ' - < ! ' 5 ! $ ! b - b k $ ! ! " " + - 3 3 / 3 3 - 3 3 5 - 3 5 / 3 - - 5 interrupt control register intc0 2 - 3 ' ! ! / ! " ! / < ! - < , ! " ! / < ! - < ! " ! / < ! - < . " ! = b - b 3 ' ! ! / ! " j a / < ' - < ! ' , j a / < ' - < ! ' j a / < ' - < ! ' . " ! = b - b + - 3 3 , 3 / / 5 , 5 5 interrupt control register intc1 ht49ra1/HT49CA1 rev. 1.00 33 may 7, 2008 timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer in - terrupt enable bit, et0i, et1i must first be set. an actual timer/event counter interrupt will take place when the relevant timer/event counter request flag, t0f, t1f is set, a situation that will occur when the relevant timer/event counter overflows. when the interrupt is en - abled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 0ch, 10h, will take place. when the in - terrupt is serviced, the timer interrupt request flag, t0f, t1f will be automatically reset and the emi bit will be au - tomatically cleared to disable other interrupts. time base interrupt for a time base interrupt to occur the the global inter - rupt enable bit, emi, and the corresponding internal in - terrupt enable bit, which is bit 1 of the intc1 register, known as etbi, must be first set. an actual time base interrupt will be generated when the time base interrupt request flag is set which is bit 5 of the intc1 register and known as tbf. this will occur when when a time-out signal is generated from the time base. when the mas - ter interrupt global enable bit is set, the stack is not full and the corresponding time base interrupt enable bit is set, an internal time base interrupt will be generated when a time-out signal is generated from the time base. this will create a subroutine call to location 014h. when a time base interrupt occurs, the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fixed time periods. the time base interrupt clock source orig- inates from the internal clock source f s . this f s input clock first passes through a divider, the division ratio of which is selected by configuration options to provide longer time base interrupt periods. the time base in - terrupt time-out period ranges from 2 12 /f s ~2 15 /f s . the clock source that generates f s , which in turn controls the time base interrupt period, can originate from three dif - ferent sources, the rtc oscillator, watchdog timer os - cillator or the system oscillator/4, the choice of which is determine by the f s clock source configuration option. real time clock interrupt for a real time clock interrupt to occur the global inter - rupt enable bit, emi, and the corresponding internal in - terrupt enable bit, which is bit 2 of the intc1 register, known as erti, must be first set. an actual real time clock interrupt will be generated when the real time clock interrupt request flag is set which is bit 6 of the intc1 register and known as rtf. when the master in - terrupt global enable bit is set, the stack is not full and the corresponding real time clock interrupt enable bit is set, an internal real time clock interrupt will be gen - erated when a time-out signal occurs, a subroutine call to location 018h will be created. when a real time in - terrupt occurs, the emi bit will be cleared to disable other interrupts. similar in operation to the time base interrupt, the pur - pose of the rtc interrupt is also to provide an interrupt signal at fixed time periods. the rtc interrupt clock source originates from the internal clock source f s . this f s input clock first passes through a divider, the division ratio of which is selected by programming the appropri- ate bits in the rtcc register to obtain longer rtc inter- rupt periods whose value ranges from 2 8 /f s ~2 15 /f s . the clock source that generates f s , which in turn controls the rtc interrupt period, can originate from three different sources, the rtc oscillator, watchdog timer oscillator or the system oscillator/4, the choice of which is deter- mine by the f s clock source configuration option. note that if the rtc oscillator is selected as the system clock, then f s , and correspondingly the rtc interrupt, will also have the rtc oscillator as its clock source. a ! a ! " ! a ; 2 ! a ! " ! ' 0 / 0 f 0 / ) a , ! " 0 / 0 a f 0 / ) a time base interrupt a ! a ! " ! a ; 2 ' 0 f 0 / ) 7 8 a ! " 0 a f 0 / ) a 0 f - rtc interrupt ht49ra1/HT49CA1 rev. 1.00 34 may 7, 2008 ( ! a $ ( ! 3 ! ! ? # $ ! " ! 3 9 ! ! " j 5 3 5 / 3 3 - 3 ' ! ! - ! " j 5 - 5 3 3 / 3 - 3 ' ! ! / ! " j 5 / 5 3 / , ! " j 5 , 5 3 , 3 9 ! ! " j 5 3 5 - ! " j 5 5 3 3 interrupt structure note that the rtc interrupt period is controlled by both configuration options and an internal register rtcc. a configuration option selects the source clock for the in- ternal clock f s , and the rtcc register bits rt2, rt1 and rt0 select the division ratio. note that the actual divi- sion ratio can be programmed from 2 8 to 2 15 . for details of the actual rtc interrupt periods, consult the rtcc register section. note after a wake-up the system requires 1024 clock cy- cles to resume normal operation. programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc0, intc1 registers until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con- trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. ht49ra1/HT49CA1 rev. 1.00 35 may 7, 2008 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. 3 % ! ! - 6 4 % power-on reset timing chart 3 % % - 6 / 5 / - - basic reset circuit 3 - 6 / 5 / - - % % - 6 - / 5 / - enhanced reset circuit ht49ra1/HT49CA1 rev. 1.00 36 may 7, 2008 res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the bat - tery, the lvr will automatically reset the device inter - nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack ! ! wdt time-out reset during normal operation timing chart wdt time-out reset during power down timing chart # % ! ! low voltage reset timing chart 3 ! ! - 6 4 % - 6 2 % res reset timing chart ht49ra1/HT49CA1 rev. 1.00 37 may 7, 2008 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu rtcc 00 0111 00 0111 00 0111 uu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1 0000 1 0000 1 uuuu u tmr1h xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1 0000 1 0000 1 uuuu u pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1 1 1 u pcc 1 1 1 u pd 1111 1111 1111 uuuu intc1 000 000 000 000 000 000 uuu uuu lcdc 0000 11 0000 11 0000 11 0000 uu u stands for unchanged x stands for unknown stands for unimplemented ht49ra1/HT49CA1 rev. 1.00 38 may 7, 2008 oscillator the one methods of generating the system clock are: external rc oscillator more information regarding the oscillator is located in application note ha0075e on the holtek website. external rc oscillator as an rc oscillator is used, an external resistor be - tween osc1 and vss is required whose value should be 12k for a frequency of 4mhz. the rc oscillator pro - vides a 3% accuracy, the conditions are: v dd =2.0v~3.6v temp.= 0 c~50 c f sys =4mhz external rtc oscillator when the microcontroller enters the power down mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the power down mode. to do this, another clock, independent of the system clock, must be provided. to do this a configuration option exists for a real time clock - rtc oscillator. here the osc3 and osc4 pins, should be connected to a 32768hz crystal to implement this internal rtc oscillator. however, for some crystals, to ensure oscillation and accurate fre - quency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specifica - tion. the external parallel feedback resistor, rp, is nor - mally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, rf typical values @ 5v, 25 c ca cb rf tbd tbd tbd rtc oscillator internal component values rtc oscillator c1 and c2 values crystal frequency c1 c2 cl 32768hz tbd tbd tbd note: 1. c1 and c2 values are for guidance only. 2. cl is the crystal manufacturer specified load capacitor value. 32768 hz crystal recommended capacitor values / rc oscillator 1 2 a ! ! / 0 " . < " ! ! j 6 1 0 + * ? i external rtc oscillator ht49ra1/HT49CA1 rev. 1.00 39 may 7, 2008 during power up there is a time delay associated with the rtc oscillator waiting for it to start up. a bit in the rtcc register, known as the qosc bit, is provided to give a quick start-up function and can be used to mini - mise this delay. during a power up condition, this bit will be cleared to 0 which will initiate the rtc oscillator quick start-up function. however, as there is additional power consumption associated with this quick start-up func - tion, to reduce power consumption after start up takes place, it is recommended that the application program should set the qosc bit high about 2 seconds after power on. it should be noted that, no matter what condi - tion the qosc bit is set to, the rtc oscillator will always function normally, only there is more power consump - tion associated with the quick start-up function. watchdog timer oscillator the wdt oscillator is a fully integrated free running rc oscillator with a typical period of 90 s at 3v, requiring no external components. it is selected via configuration op - tion. if selected, when the device enters the power down mode, the system clock will stop running, however the wdt oscillator will continue to run and keep the watch - dog function active. however, as the wdt will consume a certain amount of power when in the power down mode, for low power applications, it may be desirable to disable the wdt oscillator by configuration option. power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the halt mode or sleep mode. when the device enters this mode, the nor- mal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consump - tion to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requir - ing a full reset. this feature is extremely important in ap - plication areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi - nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. this also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as out - puts. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port b a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. ht49ra1/HT49CA1 rev. 1.00 40 may 7, 2008 each pin on port b can be setup via an individual config - uration option to permit a negative transition on the pin to wake-up the system. when a port b pin wake-up oc - curs, the program will resume execution at the instruc - tion following the halt instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program mal- functions or sequences from jumping to unknown loca- tions, due to certain uncontrollable external events such as electrical noise. it operates by providing a device reset when the wdt counter overflows. the wdt clock is sup - plied by one of three sources selected by configuration option: its own self contained dedicated internal rtc os - cillator, wdt oscillator or f sys /4. note that if the wdt configuration option has been disabled, then any instruc - tion relating to its operation will result in no operation. in the remote type with lcd series of microcontrollers, all watchdog timer options, such as enable/disable, wdt clock source and clear instruction type all selected through configuration options. there are no internal reg - isters associated with the wdt in the remote type mcu with lcd series. one of the wdt clock sources is an internal oscillator which has an approximate period of 90 s at a supply voltage of 3v. however, it should be noted that this specified internal clock period can vary with vdd, temperature and process variations. the other wdt clock source option is the f sys /4 clock. whether the wdt clock source is its own internal wdt oscillator, or from f sys /4, it is further divided by 16 via an internal 15-bit counter and a clearable single bit counter to give longer watchdog time-outs. as this ratio is fixed it gives an overall watchdog timer time-out value of 2 15 /f s to 2 16 /f s . as the clear instruction only resets the last stage of the divider chain, for this reason the actual divi - sion ratio and corresponding watchdog timer time-out can vary by a factor of two. the exact division ratio de - pends upon the residual value in the watchdog timer counter before the clear instruction is executed. it is im - portant to realise that as there are no independent inter - nal registers or configuration options associated with the length of the watchdog timer time-out, it is com - pletely dependent upon the frequency of f sys /4, the in - ternal wdt oscillator or rtc oscillator. if the f sys /4 clock is used as the wdt clock source, it should be noted that when the system enters the power down mode, then the instruction clock is stopped and the wdt will lose its protecting purposes. for systems that operate in noisy environments, using the internal wdt oscillator is strongly recommended. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how - ever, if the system is in the power down mode, when a wdt time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instruc - tions and the third is via a halt instruction. ! a ! " ! " ! a ! " ! # / 5 # 0 5 # 0 / ) a f 0 / * a / ) ! 0 / 0 ! ! a a ; 2 watchdog timer ht49ra1/HT49CA1 rev. 1.00 41 may 7, 2008 there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. all options must be defined for proper system function, the details of which are shown in the table. item options i/o options 1 pb0~pb7: wake-up enable or disable (bit option) 2 pc0: cmos output or carrier output (bit option) 3 pc0: pull-high enable or disable (bit option) lcd options 4 lcd clock: f s /2 2 ,f s /2 3 ,f s /2 4 ,f s /2 5 ,f s /2 6 ,f s /2 7 ,f s /2 8 5 lcd duty: 1 / 2, 1/3, 1/4 6 lcd bias: 1 / 2, 1/3 7 lcd segment 12~15 output or cmos output(nibble option) 8 lcd segment 16~19 output or cmos output(nibble option) interrupt options 9 int0 function: enable or disable 10 triggering edge: rising, falling or both 11 int1 function: enable or disable 12 triggering edge: rising, falling or both oscillator options 13 f s internal clock source: rtc oscillator, wdt oscillator or f sys /4 timer options 14 timer/event counter 0 clock source: f sys or f sys /4 time base options 15 time base division ratio: f s /2 12 ,f s /2 13 ,f s /2 14 ,f s /2 15 watchdog options 16 wdt enable or disable 17 clrwdt instructions: 1 or 2 instructions application circuits ht49ra1/HT49CA1 rev. 1.00 42 may 7, 2008 item options lvd/lvr options 18 lvd function: enable or disable 19 lvr function: enable or disable 20 lvr/lvd voltage: 2.1v/2.2v or 3.15v/3.3v carrier options 21 carrier duty: 1 / 2 duty or 1 / 3 duty 22 carrier frequency: f sys /8, f sys /16, f sys /32, f sys /64 for 1 / 2 duty cycle 23 carrier frequency: f sys /12, 1/3 duty cycle 24 carrier frequency: f sys /24, f sys /48, f sys /96 for 1/2 duty or 1 / 3 duty cycle - 3 & - f 1 3 & 1 , - . - , / . / , 0 - , 1 / , 2 f , + ( - f ( + - 3 3 - 6 / 5 / - - % % - 6 / 5 % + / $ $ " # 1 2 - f 1 3 & 1 0 3 & 2 f 3 & 1 / # ( . 3 # - 3 % 0 0 - f / / - - 5 1 1 / % / 0 % / % 0 - 6 / 5 - 6 / 5 - 6 / 5 ht49ra1/HT49CA1 rev. 1.00 43 may 7, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. ht49ra1/HT49CA1 rev. 1.00 44 may 7, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z ht49ra1/HT49CA1 rev. 1.00 45 may 7, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht49ra1/HT49CA1 rev. 1.00 46 may 7, 2008 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht49ra1/HT49CA1 rev. 1.00 47 may 7, 2008 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht49ra1/HT49CA1 rev. 1.00 48 may 7, 2008 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht49ra1/HT49CA1 rev. 1.00 49 may 7, 2008 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht49ra1/HT49CA1 rev. 1.00 50 may 7, 2008 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht49ra1/HT49CA1 rev. 1.00 51 may 7, 2008 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht49ra1/HT49CA1 rev. 1.00 52 may 7, 2008 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht49ra1/HT49CA1 rev. 1.00 53 may 7, 2008 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht49ra1/HT49CA1 rev. 1.00 54 may 7, 2008 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht49ra1/HT49CA1 rev. 1.00 55 may 7, 2008 package information 52-pin qfp (14 14) outline dimensions symbol dimensions in mm min. nom. max. a 17.3 17.5 b 13.9 14.1 c 17.3 17.5 d 13.9 14.1 e 1 f 0.4 g 2.5 3.1 h 3.4 i 0.1 j 0.73 1.03 k 0.1 0.2 0 7 ht49ra1/HT49CA1 rev. 1.00 56 may 7, 2008 1 4 2 - ) 0 / 0 + / 1 ( , / 2 0 * 3 5 & ? l e 64-pin lqfp (7 7) outline dimensions symbol dimensions in mm min. nom. max. a 8.9 9.1 b 6.9 7.1 c 8.9 9.1 d 6.9 7.1 e 0.4 f 0.13 0.23 g 1.35 1.45 h 1.6 i 0.05 0.15 j 0.45 0.75 k 0.09 0.20 0 7 ht49ra1/HT49CA1 rev. 1.00 57 may 7, 2008 2 2 4 1 1 1 0 * 2 / / * / + ( , 3 5 & ? l e ht49ra1/HT49CA1 rev. 1.00 58 may 7, 2008 copyright 2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com |
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